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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>MOV (array to vector, two registers)</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">MOV (array to vector, two registers)</h2><p>Move two ZA single-vector groups to two vector registers</p>
      <p class="aml">The instruction operates on two ZA single-vector groups. The vector numbers forming the single-vector group within each half of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half the number of ZA array vectors.</p>
      <p class="aml">The <span class="arm-defined-word">vector group</span> symbol VGx2 indicates that the instruction operates on two ZA single-vector groups.</p>
      <p class="aml">The preferred disassembly syntax uses a 64-bit element size, but an assembler should accept any element size if it is used consistently for all operands. The <span class="arm-defined-word">vector group</span> symbol is preferred for disassembly, but optional in assembler source code.</p>
      <p class="aml">This instruction is unpredicated.</p>
    <p>
        This is an alias of
        <a href="mova_mz_za2.html">MOVA (array to vector, two registers)</a>.
        This means:
      </p><ul><li>
          The encodings in this description are named to match the encodings of
          <a href="mova_mz_za2.html">MOVA (array to vector, two registers)</a>.
        </li><li>The description of <a href="mova_mz_za2.html">MOVA (array to vector, two registers)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul>
    <p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td colspan="2" class="lr">Rv</td><td class="l">0</td><td>1</td><td class="r">0</td><td class="l">0</td><td class="r">0</td><td colspan="3" class="lr">off3</td><td colspan="4" class="lr">Zd</td><td class="lr">0</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="MOV_mova_mz_za2_1"/><p class="asm-code">MOV     { <a href="#sa_zd1" title="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a>.D-<a href="#sa_zd2" title="Second destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd2&gt;</a>.D }, ZA.D[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offs" title="Vector select offset [0-7] (field &quot;off3&quot;)">&lt;offs&gt;</a>{, VGx2}]</p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="mova_mz_za2.html#mova_mz_za2_1">MOVA</a>    { <a href="#sa_zd1" title="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a>.D-<a href="#sa_zd2" title="Second destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd2&gt;</a>.D }, ZA.D[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offs" title="Vector select offset [0-7] (field &quot;off3&quot;)">&lt;offs&gt;</a>{, VGx2}]</p>
          <p class="equivto">
          and is always the preferred disassembly.
        </p>
        </div>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zd1&gt;</td><td><a id="sa_zd1"/>
        
          <p class="aml">Is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zd2&gt;</td><td><a id="sa_zd2"/>
        
          <p class="aml">Is the name of the second destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2 plus 1.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Wv&gt;</td><td><a id="sa_wv"/>
        
          <p class="aml">Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;offs&gt;</td><td><a id="sa_offs"/>
        
          <p class="aml">Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="mova_mz_za2.html">MOVA (array to vector, two registers)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
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